This invention generally relates to electronics and more particularly to buffer circuits for low dropout regulators.
In low voltage, low dropout linear voltage regulators (LDO), a large pass device (typically a FET) must be used to deliver high currents to a load. The size of this pass device results in a large parasitic capacitance seen from the gate of the device to AC ground. This capacitance must be charged and discharged as the load changes in order to keep the output voltage of the LDO constant. The performance of the LDO is therefore limited by how fast this capacitance can be charged and discharged (slew rate).
Additionally, the presence of the large parasitic capacitance results in a significant pole in the frequency response of the amplifier, which can make the amplifier more difficult to stabilize.
In most LDO amplifiers a source follower (or emitter follower) is used to drive the gate of the pass FET. Typical class A followers are slew rate limited in one direction by the biasing current source.
Prior art solutions to this problem typically involve using large amounts of quiescent current to decrease the output impedance of the driver (follower) and to push the gate pole to a higher frequency. Also, many other prior art designs achieve improved slew rate performance by increasing the bias current through the driver.
A buffer/driver for low dropout regulators (LDO) uses a feedback amplifier with low output impedance to drive the gate of the pass device of the regulator. This effectively pushes the gate pole out to a higher frequency. The feedback amplifier is designed for very high slew rate and high bandwidth while running at very low quiescent current. The circuit enhances the LDO performance, stability, and slew rate.